Frequency selector and synthesizer

ABSTRACT

A system for synthesizing a plurality of mutually coherent electrical signals with means for selecting the frequency of each signal.

United States Patent Honey et al.

FREQUENCY SELECTOR AND SYNTHESIZER Inventors: Francis J. Honey; Frank D. Wells,

both of Denver, Colo.

Assignee: Computer Image Cnrporation,

Denver, Colo.

Filed: Sept. 16, 1970 Appl. No.: 72,642

References Cited UNITED STATES PATENTS 3,510,865 5/1970 Callahan et al. 340/324 A 3,483,547 12/1969 Henderson ..'....'...340/324 A 3,587,083 6/ 1971 Tubinis .340/324 Primary Examiner-John W. Caldwell Assistant Examiner-Marshall M. Curtis Attorney-Rogers, Ezell, Eilers 8:. Robbins [57] ABSTRACT US. Cl. .340 324 A 235 19 Int Cl (306 2, A system for synthesizing a plurality of mutually 1 I coherent electrical Signals with means for Selecting the 7 Field of Search .....340/324 A, 315/18, 235/197, frequency of each signal 44 Claims, 8 Drawing Figures X TAL OSCILLATOR m MHZ SYNTHES/ZER FREQUENCY SELECTOR ,20 ,22 7 ,z4 1e 25 2e ,J I DIGITAL o DIGITAL OPERA- 5 M COUNT'ER ENE a 2 11 2* M SELECTOR 36% METWORK VE RT ER FREQUENCY SELECTOR PATENTE DSEP 5 m2 SHEET U 0F 6 mwm QT TORNEYS FREQUENCY SELECTOR AND SYNTHESIZER BACKGROUND OF THE INVENTION tion of the other master synthesizer signals. The complement signals provide the pulses to be added, and the ample, by using coherent synthesized frequencies for animation signals as described in Lee Harrison III patent application, Ser. No. 882,125, filed Dec.v 4, 1969, the generated image can be made to rotate at a constant rate, and that rate can be set within a wide range of rates by appropriately selecting the frequencies of the animation signals. This invention provides a system for generating such signals.

SUMMARY THE INVENTION bodiment hereinafter described uses a MHz master oscillator. The master frequency is fed into a master synthesizer which generates nine separate frequencies. Where the master frequencyis 10 MHz the master synthesizer generates frequencies in 1 MHz increments from 1 to 9 MHz. The master synthesizer includes a decase counter which generates signals corresponding to the ls bit, 2s bit, 4 s bit, and 8s bit of the Binary Coded Decimal (BCD) encoded count. These signals are then combined in a logic circuit to generate the nine synthesized frequencies. The synthesized frequencies are fed into a digital frequency selector which includes a plurality of logic switches each having switch positions zero through 9. All of the synthesized frequencies from 1 to 9 MHz are fed as inputs into the logic switches; hence, each of the logic switches may be set to gate any one of the nine frequencies to its output. With the exception of the first logic switch, the output signal of each of the logic switches is fed into a division network which divides the output signal by some-factor of 10; the output of the second logic switch being divided'by 10; the output of the third logic switch being divided by 100; and so on, to the output of the last logic switch which is divided by 10 to. the n--1 where n is the total number of logic switches. The outputs of the first logic switch and the division networks are added together to give the resultant synthesized frequency which corresponds to the frequency selected on the logic switches. For example, if the master frequency is 10 MHz, and seven logic switches are used, any frequency from 1 Hz to 9.999,999 MHz can be selected. The resultant synthesized frequency can be used as the input to an up-down counter to generate a triangular wave which can then be fed. into a digital-to-analog converter to generate a synthesized sine wave.

The adder circuitry represents a novel feature of this invention in providing a means for adding the various frequency components together to generate the synthesized frequency. The adder circuit makes use of complement and enable signals which are generated by the master synthesizer simultaneously with the generaenable signals tell the system when the pulses should be added.

Any number of digital frequency selectors can be used in conjunction with the master synthesizer togenerate a plurality of mutually coherent synthesized frequencies, each frequency different from another of the frequencies by a constant. Hence, this invention provides a novel system for generating a plurality of mutually coherent signals selected from a wide range of frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a general block diagram of the system of I this invention;

FIGS. 2 and 2A are logic diagrams of the master synthesizer of this invention;

FIG. 3 is a drawing of the waveform generated by the network of FIGS. 2 and 2A;

FIG. 4 is'a block diagram of the digital selector of this invention;

FIG. 5 is a schematic diagram of the of this invention;

FIG. 6 shows waveforms used in explaining the operation of the network of FIG. 5; and

FIG. 7 is a schematic diagram of the network for producing stairstep and sinusoidal waveforms from the synthesized digital signals from the digital frequency selector of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT I Referring to FIG. 1 of the drawing there is shown a general block diagram of the system of this invention. A crystal oscillator 10 generates a fixed frequency which will be referred to as the master frequency. While the master oscillator frequency dependson the frequency adder maximum synthesized frequency desired from the 1 cies at its output at 1 MHz intervals from 1 to 9 MHz.

The synthesized output frequencies are fed into frequency selectors 14, 16 and 18. While only three frequency selectors are shown, any number can be connected in parallel, the number of selectors depending on the number of coherent synthesized frequencies required. As the frequency selectors are identical, only the frequency selector 16 will be further described.

The synthesized frequencies from the master synthesizer 12 are fed into a digital frequency selector 20, the output of which is a series of digital pulses of the frequency selected. The digital output from the'digital frequency selector 20 is fed into an up-down counter 22 which generates a set of binary weighted outputs that are fed into a digital-to-analog converter. 24. The output of the digital-to-analog converter 24 is fed into an operational amplifier 25 (See FIG. 7) the output of which is a staircase waveform which approximates a triangular wave. This waveform is fed into a sine-shaping network 26 to generate a sinusoidal waveform having a frequency f frequency coherent with the output frequencies of the other frequency selectors.

MASTER SYNTI-IESIZER The logic diagram of the master synthesizer 12 is shown in FIG. 2. The MHz signal from the master oscillator 10 is fed through a conductor to an inverter 32. The output from the inverter 32 is fed through a conductor 34 'and'a conductor 36 to the input of an inverter 38. The output from the inverter 38 is fed through a conductor 40 and a conductor 42 to the input of a binary coded decimal (BCD) counter, having outputs Q Q Q and. Q The waveforms of these outputs are shown in FIG. 3. The master frequency waveform is shown by the waveform'50, the Q waveform is shown by the waveform 52, the Q waveform is shown by the waveform 5.4, the Q waveform is shownby the waveform56, and the Q waveform is shown by the waveform; 58., The Q, through '0 waveforms represent the ls bit, 2.s bit, 4s bit, and 8s bit; respectively. The Q v output is not used in this system. As will be seen, it is from the waveforms -58 that the frequencies of I through 9 MHz are synthesized.

The re-inverted output on the conductor 40 is also fed through a conductor and a conductor 62 to the input of an inverter 64. The output of the inverter 64 represents the inverse of the 10 MHz master frequency which is fed through a conductor 66. The signal on the conductor 60 is also fed through a conductor 68 and a conductor 70 to the input a of a NAND gate 72. The signal on the conductor 68 is also fedthrough a conductor 74 and a conductor 76 to the input a of a NAND gate 78. The signal on the conductor 74 is also fed through a conductor 80 and a conductor 82 to the input a of a NAND gate 84. The signal on the conductor 80 is also fed through a conductor 86 to the input a of a NAND gate 88.

The signal at the output Q 'of the BCD counter 44,

represented by the waveform 52, is fed through a conductor 90, aconductor 92, and a conductor 94 to the input a of a NAND gate 96. The signal on the conductor 92 is also fed through a conductor 98, and a conductor to the input a of a NAND gate 102. The signal on the conductor 98 is also fed through a conductor 104 and a conductor 106 to the input a of a NAND gate 108. The signal on the conductor 104 is also fed througha conductor 110 to the input 12 of a NAND gate 112;

The Q output from the BCD counter 44,.

represented by the waveform 58, is fed through a conductor 120, a conductor 122, and a conductor 124 to the input a of the NAND gate 112. The NAND gate 112 NANDs the waveforms Q and Q with the resultant output being fed through a conductor 126 and a conductor 128 to the input of an inverter 130. The output of the inverter 130 is fed through a conductor 1.32 to the input b of the NAND gate 72 which NANDs the signal on the conductor 132 with the master oscillator waveform. 50. The output of the NAND gate 72 which is an inverted 1 MHz signal shown by the waveform 136 of FIG. 3, is fed through a conductor 137.

The Q, signal from the BCD counter 44, represented by the waveform 54 of FIG. 3, is fed through a conductor 140, a conductor 142 and a conductor 144 to the input b of the NAND gate 108. The output of the NAND gate 108 is fed through a conductor 146 and a conductor 148 to the input of an inverter 150. The output from the. inverter 150 is fed through a conductor 152 to the input b of the NAND gate 78 which NANDs the signal on the conductor 152 with the master oscillator signal. The output from the NAND gate 78 which is an inverted 2 MHz signal shown by the waveform 154 of FIG. 3, is fed through a conductor 156.

The 0 signal on the conductor 140 is also fed I through a conductor 158 to the input of an inverter 160. The output from-the inverter 160 represents the inverse of the Q signal 0:6,. Thefi; signal from the inverter 160 is fed through a conductor 162 and a conductor 164 to the input b of the NAND gate 102. The

NAND gate 102 NANDs the Q, and T); signals. The 7 output of the NAND gate 102 is fed through a conductor 166 and a conductor 168 to the input of an inverter 170. The output from the inverter 170 is fed through a conductor 172 to the input b of the NAND gate '84 which NANDs the signal on the conductor 172 with the master oscillator signal to produce at its output an inverted 3 MHz signal as shown by the waveform of FIG. 3. This inverted 3 MHz signal is fed through a conductor 182. v

The 0., signal on the conductor 120 is also fed through a conductor 186 to the input of an inverter 188. The output of the inverte 188 represents the inverse of the Q waveform or Q and is fed through a conductor 190 and a conductor 192 to the input b of the NAND gate 96 which NANDs the (I; and Q signals. The output from the NAND gate 96 is fed through a conductor 194 and aconductor 196 to the input of an inverter 198. The output of the inverter 198 is fed through a conductor 200 to the input b of the NAND gate 88 which NANDs the signal on the conductor 200 with the master oscillator signal to produce at its output an inverted 4 MHz signal as shown by the waveform 202 of FIG. 3. This signal is fed through a conductor 204. I

The signal on the conductor 34 from the inverter 32, which is an inverted master oscillator signal, is also fed through a conductor 210 and a conductor 212 to the input of an inverter 214, the output of which is fed through a conductor 216 and a conductor 218 to the input a of a NAND gate 220. The signal on the conductor 216 is also fed through a conductor 222 and a conductor 224 to the input a of a NAND gate 226. The signal on the conductor 222 is also fed through a conductor 228 to the input a of the NAND gate 230. The signal on the conductor 216 is also fed through a conductor 232 and a conductor 234 to the input a of a NAND gate 236. The signal on the conductor 232 is also fed through a conductor 238 and a conductor 240 to the input a of a NAND gate 242. The signal on the conductor 238 is also fed through a conductor 244 to the input a of a NAND gate 246. The 0 signal from the BCD counter 44 on the conductor 90 is also fed through a conductor 250 to the input b of the NAND gate 230 which NANDs the Q, signal and the master oscillator signal to produce an inverted 5 MHz signal at its output as shown by the waveform 252 of FIG. 3.

The waveform 252 is fed through a conductor 254. The signal from the NAND gate 96 on the conductor 194 is also fed through a conductor 256 to the input b of the NAND gate 226 to produce at its output an inverted 6 MHz signal as shown by the waveform 258 of FIG. 3. This signal is fed through a conductor 260. The signal from the NAND gate 102 on the conductor 166 is also fed through a conductor 262 to the input b of the NAND gate 220 to produce at its output an inverted 7 MHz signal as shown by the waveform 264 in FIG. 3. This signal is fed through a conductor 266. The signal from the output of the NAND gate 108 on the conductor 146 is also fed through a conductor 268 to the input b of the NAND gate 236 to produce an inverted 8 MHz signal at its output as shown by the waveform 270 of FIG. 3. This signal is fed through a conductor 272. The output signal from the NAND gate 1 12 on the conductor 126 is also fed through a conductor 27410 the input b of the NAND gate 242 to produce at its output an inverted 9 MHz signal as shown by the waveform 276 of FIG. 3. This signal is fed through a conductor 278.

It can be seen that the frequencies of 1 through 9' MHz have been synthesized from a single master oscillator signal of MHz by the circuit of FIG. 2.

For reasons which will be hereinafter described, 1 through 9 MHz waveforms are generated with their pulses advanced in time by one master oscillator pulse. These waveforms are also shown in FIG. 3 and are used as Enable signals. Hence, the waveform 300 is an inverted 1 MHz signal corresponding to the waveform 136 advanced one master oscillator pulse; the waveform 301 is an inverted 2 MHz signal corresponding to the waveform 154 advanced one master oscillator pulse; the waveform 302 is an inverted 3 MHz signal corresponding to the waveform 180 advanced one master oscillator pulse; the waveform 303 is an inverted 4 MHz signal corresponding to the waveform 202 advanced one master oscillator pulse; the waveform 304 is an inverted 5 MHz signal corresponding to the waveform 252 advanced one master oscillator pulse; the waveform 305 is an inverted 6 MHz signal corresponding to the waveform 258 advanced one master oscillator pulse; the waveform 306 is an inverted 7 MHz signal corresponding to the waveform 264 advanced one master oscillator pulse; the waveform 307 is an inverted 8 MHz signal corresponding to the waveform 270 advanced one master oscillator pulse; and the waveform 308 is an inverted 9 MHz signal corresponding to the waveform 276 advanced one master 2scillator pulse. The waveforms 300-308 are labeled E through E; respectively, and are used as enable signals for telling the system when a pulse should be added. This will be explained in more detail in descriaing the frequency adders of this system.

The E through E; waveforms are generated by inverting the Q, waveform which advances the I through 9 MHz waveforms by one master oscillator pulse. Hence, the Q waveform on the conductor 90 at the Q output of the BCD counter 44 is also fed through a conductor 320 and a conductor 322 to the input of an in! verter 324 (FIG. 2A). The inverter 324 inverts the Q waveform 52 to advance the 1 through 9 Ml-Iz waveforms by one master oscillator pulse. The Q output from the inverter 324 is fed through a conductor 326 and a conductor 328 to the input a of a NAND gate 330. The signal on the conductor 326' is also fed through a conductor 332 and a conductor 334 to the signal with the Q signal. The output of the NAND gate input a of the NAND gate 336. The signal on the conductor 332 is also fed through a conductor 338 and a conductor 340 to the input a of a NAND gate 342. The

signal on the conductor 338 is also fed through a conductor 344 to the input a of a NAND gate 346.

The inverted master oscillatorsignal at the output of the inverter 32 which is fed through the conductors 34 and 210 is also fed through a conductor 362 to the input of an inverter 364. The output of the inverter 364 is fed through a conductor 366 and a conductor 368 to the input a of a NAND gate 369. The signal on the conductor 366 is also fed through a conductor 370 and a conductor 372 to a NAND gate 374. The signal on the conductor 370 is also fed through a conductor 376 and a conductor 378 to the input a of the NAND gate 380. The signal on the conductor 376 is also fed throughv a conductor 382 and a conductor 384 to the input a of a NAND gate 386. The signal on the conductor 382 is also fed through a conductor 388 and a conductor 390 to the input a of a NAND gate 392. The signal on the conductor 388 is also fed through a conductor 394 and a conductor 396 to the inputa of aNAND gate 398. The signal on the conductor 394 is also fed through a conductor 400 and a conductor 402 to the input a of a NAND gate 404. The signal on the conductor 400 is also fed through a conductor 406 and a conductor 408 to the input a of a NAND gate 410.

The 0., output from the BCD counter 44 on the conductor 122 is also fed through a conductor 411 to the input b of the IiAND gate 330 which NANDs the O 330 is fed through a conductor 412 and a conductor 413 to the input of an inverter 414. The output from the inverter 414 is fed through a conductor 415 to the input b of the NAND gate 369. The NAND gate 369 NANDs the signal on the conductor 415 with the master oscillator signal of the conductor 368 to produce at i2 output conductor 420 the inverted 1 MHz signal, E shown by the waveform 300 of FIG. 3.

The Q output from the BCD counter 44 on the conductor 142 is also fed through a conductor 422 to the input b of the N AND gate 336 which NANDs the Q signal with the Q signal. The output from the NAND gate 336 is fed through a conductor 424 and a conductor 426 to the input of an inverter 428. The output from the inverter 428 is fed through a conductor 430 to the input b of the NAND gate 374 which NANDs the signal on the conductor 430 with the master oscillator sig l to produce at its output an inverted 2 MHz signal, E represented by the waveform 301.

The 6 signal at the output of the inverter which is fed through the conductor 162 is also fed through a conductor 434 to the input b of the NAND gate 342 which NANDs the Q signal with the Q signal. The output of the NAND gate 342 is fed through a conductor 436 and a conductor 438 to the input of an inverter 440. The output of the inverter 440 is fed through a conductor 442 to the input b of the NAND gate 380 which NANDs the signal on the conductor 442 with the master oscillator signal to produce at its output conductor 444 the inverted 3 MHz signal, E represented by the waveform 302.

The 0., signal from the inverter 188 which is fed through the conductor 190 is also fed through a conductor 446 to the inputb of the NAND gate 346 which NANDs the 0, signal with the 1 signal. The output from the NAND gate 346 is fed through a conductor 448 and a conductor 450 to the input of an inverter 452. The output from the inverter 452 is fed through a conductor 454 to the input b of the NAND gate 386 which NANDs the signal on the conductor 454 with the master oscillator signal to produce at its output conductor 456 the inverted 4 MHz signal, E represented by the waveform 303.

The signal on the conductor 320 is also fed through a conductor, 460 to the input of an inverter 462. The output of the inverter 462 is fed through a conductor 464 to the input b of the NAND gate 246 which NANDs the Q, signal with the master oscillator signal to produce at output conductor 466 the inverted 5 MHz signal, E represented. by the waveform The output from the NAND gate 346-which is fed through the conductor 448 is also fed through a conductor 470 .to the input b of the NAND gate 392 which NANDs the signal on the conductor 470. with the master oscillator signal to prcguce at its output 472 the inverted- 6 MHz signal, E represented by thewaveform 305. The output of theNAND gate 342 which is fed through the conductor 436 is also fed through a conductor 474 to the input bof the NAND gate 398 to produce at its output conductor 476 the inverted 7 MHz signal, E represented by the waveform 306. The output of the NAND gate 336 which is fed through the conductor 424 is also fed through a conductor 478 to the input b of the NAND gate 404 which NANDs the signal on the conductor 478 with the master oscillator signal to produce at ifs output conductor 480 the inverted 8 MHz signal, E represented by the waveform 307. The output from the NAND gate 330 which is fed through the conductor 412 isalso fed through a conductor 482 to the input b of the NAND gate 410 which NANDs the signal on the conductor 482 with the master oscillator signal to produce at i ts output conductor 484 the inverted 9 MHz signal, E represented by the waveform 308.

DIGITAL FREQUENCY SELECTOR In FIG. 4 there is shown the block diagram of the digital frequency selector of this invention. The circuit of FIG. 4 makes possible the selection of any of a wide range of frequencies. In this embodiment seven logic switches 501, 502, 503, 504, 505, 506 and 507 e are used. As the logic switches 501-507 are identical,

510, to which any on of its inputs can be selectively gated; the switch 502 has an output conductor 512 to which any one of its inputs can be selectively gated, the switch 503 has an output conductor 513 to which any one of its inputs can be selectively gated; and so on, to the switch 507 which has an output conductor 522 to which any one of its inputs can be selectively gated.

The selected signal F, at the output of the switch50l is fed through the conductor 510 to the input a of a frequency adder 530. The selected signal at the output of the switch 502 is fed through the conductor 512 to the input a a divide by 10 network 532. The network 532 divides the selected frequency on the conductor 512 by a factor of 10. The frequency F at the output of the division network 532 is fed through a conductor 534 to the input b of the frequency adder 530. The frequency adder 530 which will be hereinafter described. in detail, is a circuit which generates at its output the sum of the frequencies at its inputs a and b. The output of the frequency adder 530 is fed through a conductor 536 to the input a of a frequency adder 540.

The selected signal at the output of the switch 503 is fed through the conductor 513 to the input of a divide by 10 network 538. The network 538 divides the selected frequency on the conductor 513 by a factor of 100. The frequency F, at the output of the division network 538 is fed through a conductor 539 to the input b.

of a frequency adder 540. The output of the frequency adder 540, which is the sum of the frequencies F,+F

+1 is fed into the input a of the next frequency adder the switch 507 is fed through the conductor 522 to the input of a division network 541 which divides the sel ected frequency at the output of the switch 507 by 10.

The output frequency F from the division network 541 is fed through a conductor 542 to the input b of a frequency adder 544. The output from the preceding frequency adder is fed into the input a of the frequency adder 544. The output of the frequency adder 544 is the sum of all of the frequencies selected on the switches 501-507 and is fed through a conductor 546 to the up-down Counter 22.

The frequency adder 530 has two additional inputs which are necessary to perform the required additions. Referring again to the 1 through 9 MHz waveforms of ,FIG. 3, it should be noted that a pulse may be added to any one of the waveforms only where there is a space available. For example, referring to the waveform 136 pulses may be added anywhere on this waveform except at the end where there is already a pulse. In other words, nine pulses may be added to the waveform 136; eight pulses to the waveform 154; seven pulses to the waveform six pulses to the waveform 202; five pulses to the waveform 252; four pulses to the .waveform 258; three pulses to the waveform 264; two pulses to the waveform 270; and one pulse to the waveform 276. In this regard it should also be noted that except for the 5 MHz waveform 252 each of the other waveforms has a complement waveform. Complement waveforms are those where one has a pulse where the other has a space;therefore, the waveforms 136 and 276, 154 and 270, 180 and 264, and 202 and 258 are complement waveforms. Although the 5 MHz waveform 252 has no compl ement among the nine waveforms it is noted that the E waveform 304 is the complement of the waveform 252 since its pulses are advanced by one master oscillator pulse. Therefore, the E waveform 304 can be used as the complement of the waveform 252. Because of these complementary relationships the complement waveform is used to supply the pulses to I be added.

Referring again to FIG. 4, the switch 501, which gates the selected millionths digit frequency F7, also automatically gates the F, complementary waveform to an output conductor 550. Therefore, whatever frequency is selected on the switch 501, that frequency is gated to the output conductor 510, and the complementa'ry frequency is gated to the output conductor 550. The complementary waveform on the conductor 550 is fed into an inverter 552. The output from the inverter 552, is fed through a conductor 554, to an input 556 of the frequency adder 530, from the frequency adder 530 by 'a conductor 557 to an input 558 of the frequency adder 540, and so-on to a conductor 559 which feeds the signal to an input 560 of the last frequency adder 544. It is the complementary waveform pulses which are actually added to the selected-frequency F, by the frequency adders. The complementary waveforms are referred to as F signals. g

The system must also know when vacancies in the F, waveform will occur. By using the waveforms 300-308, the system can detect when the next F pulse will occur and, hence, when the next vacancy in theF, waveform, will occur, which is one master oscillator pulse later.

When the millionths digit frequency F, is selected by the switch 501, the appropriate E waveform is automatically gated through the switch 501 and an output conductor 561 to the input of an inverter 562. The output from the inverter 562 is fed through aconductor 564 to an input 566 of the frequency adder 530 from the frequency adder 530 by a conductor 567 to an input 568 of the frequency adder 540, and so on to a conductor 569 which feeds the signal to an input 570 of the last frequency adder 544. The signal at the output of the inverter 562 is referred to as the F signal.

Therefore, the switch 501 selects the millionths digit frequency, and the switches 502 and so on to 507 select the 100,000ths, 10,000ths, 1,000ths, lOOths, lOths, and units digit frequencies to be added. Automatically with the setting of the switch 501 to a selected F, frequency, there is gated the appropriate F A and F signals. In other words, the switches 502-507 tell the system how many pulses to add, the F A signal provides the pulses to be added, and the F E signal tells the system when to add the pulses.

FREQUENCY ADDER In FIG. 5 there is shown a detailed drawing of the frequency adders 530, 540, and so on, to 544 of this invention. In this embodiment six such frequency adders are used, although it is to be understood that the number used depends on the frequency range desired. Referring to the frequency adder 530, the selected millionth digit output frequency F, on the conductor 510 is fed to the input a of a NOR gate 650. The selected 100,000th digit frequency F on the switch 502, which is to be added to the millionth digit frequency F, is fed through the conductor 534 to the input of a differentiator circuit 652. The output from the differentiator circuit 652 is fed through a conductor 654 to the 'Ijnput of a flip-flop 656. The flip-flop 656 has Q and Q outputs and a clear input c. When the flip-flop 656 is triggered by a signal at its input T the output of the flip-flop changes state with a zero level at its Goutput and a 1 level at its Q output. The Ooutput of the flip-flop 656 is connected by a conductor 658 to the K input of a flipflop 660. The 1 level Q output signal from the flip-flop 656 is fed through a conductor 662 to the J input of the flip-flop 660. 1

The F, signal on the conductor 564 is fed through a conductor 670 to the T input of the flipflop 660. Since the J input of the flip-flop 660 has been placedat a I level by the flip-flop 656, the flip-flop '660 will change the input b of a NAND gate 684, and by a conductor I 686 to the input a of the NAND gate'674.

The F signal on the conductor 554 is fed through a conductor 690 to the input a of the NAND 678. The F signal on the conductor 554 is also fed through a conductor 692 to the input a of the NAND gate 684. With the input b of the NAND gate 678at 1 level, the output of the NAND gate 678 will go to a zero level when its input a receives the next positive pulse of the F signal. The negative output signal from the NAND gate 678, which is one master oscillator pulse in width, is fed through a conductor 700 and a conductor 702 to the input b of the NOR gate 650. Because the F is the complement of the F, waveform, the negative pulse at the input b of the NOR gate 650 occurs at precisely the same time a blank space occurs on the F, waveform at the input a of the NOR gate 650. The output of the NOR gate 650 is a waveform equal to the sum of the pulses at its input a and the pulses at its input b. The

output signal from the NOR gate 650 is fed through a conductor 710 to the input of an inverter-712. The

negative pulse at the output of the NAND gate 678 which is fed through the conductor 700v is also fed through the conductor7l4 to the input of an inverter 716. The output of the inverter 716 is fed through a conductor 718 to the input of a differentiator circuit 720, the output of which is fed through a conductor 722 and a conductor 724 to the clear input C of the flip-flop 660. The signal on the conductor 722 is also fed through a conductor 726 to the clear input C of the flip-flop 656. The output signal from the differentiator circuit 720 clears the flip-flops 656 and 660 with the Q and Q outputs of the flip-flop 656 resetting to a zero level and a 1 level, respectively. With the 6 output of the flip-flop 656 at a 1 level, the 1 level signal is fed through the conductor 658 to the K input of the flipflop 660. With the flip-flop 660 cleared and a I level at its input K, its Ooutput will go to a 1 level and its Q output to a zero level. The 1 level signal from the Q output is fed through the conductors 680 and 682 to the input b of the NAND gate 684.

Assuming that a pulse on the F signal occurs before the next F pulse on the conductor 534, the F pulse is fed through the conductor 554 and 692 to the input a of the NAND gate 684. With both inputs a and b of the NAND gate 684 at 1 levels, a zero level signal will be generated at the output for the duration of the F A pulse. This pulse is fed through a conductor 730 to the input of an inverter 732. The 1 level signal at the6output of the flip-flop 660 which is fed through the conductor 680 also is fed through the conductor 686 to the input a of the NAND gate 674.

Assuming that a pulse on the F E waveform occurs prior to the next pulse on the F waveform on the conductor 534, the positive F pulse is fed through the conductors 564 and 672 to the input b of the NAND gate 674. With both inputs a and b at a 1 level a zero level signal of a width equal tothe width of the F pulse is fed through a conductor 734 to the input of i an inverter 736. The outputs from the inverters 712, 732 and 736 are passed on to the next frequency adder 540 where the 10,000th digit frequency F set by the switch 503 is added. Hence, the added signal from the inverter 712 is fed through the conductor 536 to the input a of a NOR gate like the NOR gate 650; the output from the inverter 732 is fed through a conductor 752 to the a inputs of a NAND gate like the NAND gates 678 and 684; and the output from the inverter 736 is fed through a conductor 756 to the T input of a flip-flop like the flip-flop 660; and the input b of a NAND gate like the NAND gate 674.

The frequency adder network 540, and in fact, all of the frequency adders except the frequency adder 544,

are identical to the frequency adder network 530. The frequencies added by the frequency adder 540 will be the output frequency F, F from the frequency adder 530 and the 10,000th digit frequency F set by the switch 503 which is fed through the conductor 539 to the frequency adder 540.

As an analysis of the frequency adder network will show, the NAND gates 684 and 674 operate to insure higher frequencies take precedence over the lower frequencies. In other words, the 100,000th digit I frequency F takes precedence over the 10,000th digit frequency F and so on. Whenever a F waveform pulse occurs on the input conductor 534 it will trigger the flip-flop 656. The next occurring F pulse will trigger the flip-flop 660, disabling the NAND gates 684'and 674 so that the F and F pulses cannot feed through to the frequency adder network 540. In this way the pulses of the F waveform of the frequency adder 530 will be added to the F, waveform before the F F and so on, pulses are added. Without F and F pulses, the frequency adder network 540 will not operate, nor will the other frequency adders in the system.

The last frequency adder network 544 adds in the units frequency F selected by the switch 507. The frequency adder 544 is identical to the frequency adder 530 except that the NAND gates 684 and 674 and the inverts 732 and 736 and associated conductors are eliminated, there being no need for them in the last frequency adder. Hence, the F, frequency .is fed throughv the conductor 542 to the input b of the frequency adder 544; the F output from the previous frequency adder is fed through the conductor 569 to the input 570 of the frequency adder 544; the F signal from the previous adder circuit is fed through the conductor 559 to the input 560 of the frequency adder 544; and the frequency output signal from the previous adder representing the sum of the frequencies F through F is fed through a conductor 780 to the input a of the frequency adder 544. The signal at the output conductor 546 of the frequency adder 544 is the sum of all of the frequencies F through F and is a coherent,

number of spaces. This non-symmetry is called phase jitter. The phase jittercan be greatly reduced by dividing the resultant frequency by a factor of 10 or a factor of 100. While this divides the frequency by 100, it also divides the phase jitter by 100, which gives a much smoother waveform. If, for example, the resultant frequency is divided by then the maximum frequency'obtainable by this embodiment is 99,999.99 l-lz.

UP-DOWN COUNTER AND DIGITAL o ANALOG CONVERTER Referring to FIG. 7 there is shown the network, for

producing a staircase waveform output from the synthesized digital signal from the digital frequency selector 20. .The synthesized digital frequency on the conductor 546 is fed through a conductor 850 to the input a of a NAND gate 852. The signal on the conductor 546 is also fed through a conductor 854 to the input a of a NAND gate 856. When the NAND gate 852 is enabled the digital signal on the conductor 850 is fed through the NAND gate 852 and a conductor 858 to -the U input of the Up-down counter 22, causing the counter 22 to count up. When the NAND gate 856 is enabled the digital signal on the conductor 854 is fed through the NAND gate 856 and a conductor 862 to the D input of the up-down counter 22, causing the counter 22 to count down.

ln this embodiment of the invention the up-down counter 22 has outputs corresponding to the ls, 2's, 4s, 8s, l6s, 32s, 64s, l28sand 256s bits. The number of outputs required depends on the desired relationship between the frequency of the digital input and the triangular output. With the circuit of FIG. 7, the up-down counter 22 counts continuously up and down between counts of 6 and 506 so that for each 1,000 pulses fed to its input the up-down counter will count one full cycle, the staircase wave output having a frequency of one one-thousandth of that of the digital input. Other staircase wave frequencies could be produced by simply changing the number of input pulses necessary for the up-down counter to complete one cycle. For example, if the up-down counter 22 hadsix binary weighted outputs corresponding to the ls, 2s, 4s, 8s, l6s, and 32s bits, the counter could be made to count continuously up and down between counts of 7 and 57 so that for each 100 pulses fed to its input the counter would count one full cycle, the staircase output having a frequency of one one-hundredth of that of the digital input.

In this embodiment the up-down counter 22 has nine bits to produce necessary binary weighted output. As shown in FIG. 7, the l s bit is connected by a conductor 864, an inverter 866, a conductor 868, a conductor 870, and a conductor 872 to the input a of a NAND gate 874, and by a conductor 876 to the input a of a NAND gate 878, and by a conductor 880 to the ls bit input of the digital to analog converter24. The 2s bit output of the up-down counter 22 is connected by a conductor 884 and a conductor 886 to the input b of the NAND gate 874, and a conductor. 888 anda conductor 890 to the input b of the NAND gate 878, and a conductor 892, an inverter 894 and a conductor 896 to the 2s bit input of the digital to analog converter 24. The 4s bit output of the up-down counter 22 is connected by a conductor 898 and a conductor 900 to the input of the NAND gate 878, and a conductor 902, an inverter 904, a conductor 906, and a conductor 908 to the input 0 of the NAND gate 874, and a conductor 910 to the 4s bit input of the digital to analog converter 24. The 8s bit output of the up-down counter 22 is connected by a conductor 912 and a conductor 914 to the input d of the NAND gate 874, and by a conductor 916, an inverter 918, a conductor 920 and a conductor 922 to the input d of the NAND gate 878, and by a conductor 924 to the 8's bit input of the digital to analog converter 24. The l6s bit output of the up-down counter 22 is connected by a conductor 926 and a conductor 928 to the input e of the NAND gate 874, and by a conductor 930, an inverter 932, a conductor 934, and a conductor 936 to the input e of the NAND gate 878, and by a conductor 938 to the l6s bit input of the digital to analog converter 24. The 32s bit output of the up-down counter 22 is connected by a conductor 940 and a conductor 942 to the input f of the NAND gate 874, and by a conductor 944, an inverter 946,,a

conductor 948, and a conductor 950 to the input f of'a NAND gate 878 and by a conductor 952 to the 32s bit input of the digital to analog converter 24. The 64s bit output of the up-down counter 22 is connected by a conductor 954, and a conductor-956 to the input g of the NAND gate 874 and by a conductor 958, an inverter 960, a conductor 962, and a conductor 964 to the input 3 of the NAND gate 878, and, by a conductor 966 to the 64s bit input of the digital to analog converter 24. The 128's bit output of the up-down counter 22 is connected by a conductor 968 and a conductor 970 to the h input of the NAND gate 874, and by a conductor 972, an inverter 974, a conductor 976, and a conductor 978 to the input h of the NAND gate 878, and by a conductor 980 to the l28s.bit input of the digital to analog converter 24. The 256s bit output of the up-down counter 22 is connected by a conductor 982 and a conductor 984 to the input i of the NAND gate 874, and by a conductor 986, an inverter 988, a conductor 990, and a conductor 992 to the input i of the NAND gate 878, and by a conductor 994 to the 256s bit input of the digital to analog converter 24. The NAND gate 874 detects the count of 506, and the NAND gate 878 detects the count of 6 from the updown counter 22.

The output of the NAND gate 874 is connected by a conductor 1000 and a conductor 1002 to the S input of a flip-flop 1004, and by a conductor 1006 to the input c of the NAND gate 852. The output of the NAND gate 878 is connected by a conductor 1008 and a conductor 1010 to the R input of the flip-flop 1004, and by a conductor 1012 to the input 0 of the NAND gate 856.

The flip-flop 1004 has outputs Q and 6. The out put is connected by a conductor 1014 to the input b of the NAND gate 856, and then output is connected by a conductor 1016 to the input b of the NAND gate 852. As will be hereinafter described, the outputs from the NAND gates 874 and 878 control the state of the flip flop 1004, which controls the NAND gates 852 and 856, which control the direction of count of the updown counter 22. 1

The digital to analog converter 24, is a current summing device which produces a current at its output proportional to the binary code at its input. Hence, the

greater the count at its input, the greater the current at its output. The output of the digital to analog converter 882 is connected by a conductor 1020, a conductor 1022, a resistor 1024, and a potentiometer 1026 to a conductor 1028 that carries a positive DC voltage. The potentiometer .1026 is set so that the output current is zero when the binary input is a count of 256. In so doing, the output current level of the digital to analog converter 24 increases from zero as the binary coded input increases from 256, and decreases from zero as the binary coded input decreases from 256, producing an alternating current signal on the conductor 1020. This alternating current signal is fed through a conductor 1030 to the operational amplifier 25 to produce at its output a voltage proportional to the binary number at the input of the digital to analog converter 24. Hence, the output of the operational amplifier 25 is a waveform that increases from zero at the binary count 7 of 256 in a staircase manner to some positive peak voltage at the count of 506, then decreases in a staircase manner to some negative peak voltage at the count of 6, and then increases in a staircase manner back up to zero at the count of 256 and so on. In this way, a continuous staircase wave is generated at the output of the operational amplifier 25. Because the steps of the wave are very small, one for each count, the waveform approximates a triangular waveform. The triangular waveform at the output of the operational amplifier 25 is fed through a conductor 1034 to the sine shaping network 26 to produce a sine wave of the same frequency as the triangular wave.

OPERATION To explain the operation of thesystem suppose that it is desired to produce a signal at the output conductor 546 with a frequency of 9.932678 MHz. The millionth digit switch 501 is set on 9 to gate the 9 MHz signal P, through to the conductor 510. The 100,000th digit switch 502 is set on 9 to gate the 9 MHz signal F through to the conductor 512, and into the division network 532, where it is divided by 10 to produce a frequency of 900 KHz on the conductor 534. In this same manner the switches 503 through 507 are set to produce 30 X112, 2 KHz, 600 Hz., Hz, and 8 Hz, signals at the outputs from their dividers 538 through 541, respectively. The 9 MHz signal is gated by the switch 501 by setting the switch 501 in the 9 position. With the switch 501 in the 9 position the complementary 1 MHz signal is fed through the conductor 550, the inverter 552, ar& the conductor 554 to form the F signal. Also the E signal, which is a 1 MHz signal advanced one full master oscillator pulse relative to the F A signal, is fed through the conductor 561, the inverter 562, and the conductor 564 to form the F signal. The F F F and F signals are all inputs to the frequency adder 530.

The F signal, which is the 30 KHz signal, is fed through the conductor 539 to the input b of the frequency adder 540. Although the frequency adders for adding the 2 KHZ, 600 Hz, and 70 Hz signals F F and F respectively, are not shown, these adders have suitable inputs b for introducing these frequencies. Finally, the F signal, which is the 8 Hz signal and the last in the series, is fed through the conductor 542 to the input b of the frequency adder 544.

FIG. 6 shows the waveforms of the" adder circuit 530. The waveform 800 is the 9 MHz signal F on the conductor 510. The waveform 802 is the complement of the waveform 800 and is the 1 MHz signal F,, on the conductor 554. The waveform 804 is the l MHzsignal F;- which is advanced one full master oscillator pulse relative to the F waveform 802. The waveform 806 is the 900 KHz signalF which is set by the switch 502 and which is fed through the conductor 534. It is the frequency of the F waveform 806 that is added to the frequency of the F, waveform 800 by the adder network 530.

When the differentiator circuit 652 detects the trailing edge of the first pulse of the F6 waveform 806 it produces at its output a negative going spike as shown by the waveform 808. This negative going spike triggers the flip-flop 656 which places a 1 level at the J input of the flip-flop 660 as shown by the waveform 810. The trailing edge of the next F pulse that comes along at the T input of the flip-flop 660, triggers the flip-flop 660, placing its Q output at a 1 level as shown by the waveform 812. This 1 level is fed through the conductor 676 to the input b of the NAND gate 678. Exactly one master oscillator pulse later a pulse on the F waveform appears at the input a of the NAND gate 678. With both inputs a and b of the NAND gate 678 at a 1 level, a zero level pulse is generated at its output having a width equal to the width of the F pulse. This negative pulse is shown by the waveform 814. The negative pulse is fed to the input b of the NOR gate 650. Because F is a complement of F, the negative pulse at the input b of the NOR gate 650 occurs simultaneously with a blank space on the F waveform. The NOR gate 650 adds the negative pulse at its input b in the blank space to produce at the output of the inverter 712 the sum of the two waveforms 800 and 814 as shown by the waveform 816 of FIG. 6. The negative pulse at the output of the NAND gate 678 which is added to the waveform F is also fed through the inverter and differentiator circuit 716 and 720 to produce a spike generated at the trailing edge of the F A pulse to clear the flip-flops 656 and 660. With the 656 and 660 cleared, the input b of the NAND gate 678 goes to a zero level, the input b of the NAND gate 684 goes to a I level, and the input a of the NAND gate 674 goes to a 1 level as heretofore described. Hence, the NAND gate 678 is disabled and the NAND gates 684 and 674 are enabled.

What happens next depends on which of the waveforms F through F the next pulse occurs. Because the F frequency is considerably higher than the frequencies of the waveforms F through F it is most likely that several pulses on the F waveform will occur before an F frequency pulse-occurs. Each time the pulse on the F frequency occurs the operation heretofore described of the frequency adder $30 will repeat to add a F waveform pulse to the F waveform, each time the flip-flops 656 and 660 resetting, and the NAND gates 684 and 674 enabling. However, eventually a F waveform pulse will occur prior to an F waveform pulse. With the NAND gates 674 and 684 enabled, the F and F waveforms are gated through the NAND gates 684 and 674 and the inverters 732 and 736 to the frequency adder 540. The frequency adder 540 operates in response to the F waveform pulse'in exactly the same manner as the frequency adder 530, with the pulse on the F waveform triggering a flip-flop like the flip-flop 656 to add an F A pulse to the output waveform from the frequency adder 530, this waveform being the sum of the waveforms F and F After the pulse is added the frequency adder 540 is reset as heretofore described with NAND gates like the NAND gate 674 and 684 being enabled to gate the F and F waveforms through to the next frequency adder network. If a pulse on the F waveform is the next to occur, this adder will add a P pulse to the output waveform from the adder 540 in response to the F pulse. This process continues through to the last frequency adder 544 where F waveform pulses are added in response to pulses occurring on the F waveform, it being remembered that the NAND gates 674, 684, and 678 in each of the frequency adders insure that the higher frequencies take precedence over the lower frequencies. Therefore, in this example, over a one second period, the frequency. adder 530 adds 900,000 pulses to the F waveform; the next frequency adder 540 adds 30,000 pulses to the F waveform; the next frequency adder adds 2,000 pulses to the F waveform; the next frequency adder adds 600v pulses to the F, waveform; and the last frequency adder 544 adds eightpulses to the F waveform, giving a resultant frequency at the output conductor 546 of 9.932678 bled the digital signal is. fed to the U input of the updown counter 22 causing the up-down counter 22 to begin counting up one digit for each pulse fed to the input U When the up-down counter 22 has counted to a count of 506 the signals at its outputs will be such as to enable the NAND gate 874, producing at its output a 0 signal which is fed through the conductors 1000 and 1006 to the input 0 of the NAND gate 852, disabling the NAND gate 852 which disables the input U of the up-down counter 22 causing the counter to stop count ing. The 0 level signal on the conductor 1000 is also fed through the conductor 1002 to the S input of the flipflop 1004 placing its Q output at a 1 level and itsfioutput at a 0 level. The 1 level Q output from the flip-flop 1004 is fed through the conductor 1014 to the input b of the NAND gate 856. The zero level 6 output from NAND gate 856 each at a 1 level, the NAND gate 856 is enabled allowing the digital signal on the conductor 854 to be fed through the NAND gate 856 and the conductor 862 to the input D of the up-down counter 22 causing the up-down counter 22 to count down from acount of 506. As the digital pulses on the conductor 854 continue to feed into the input D, the up-down counter 22 continues to count down until it gets to a 6 count. When it gets to a 6 count its binary encoded outputs are such as to enable the NAND gate 878 producing atits output a level signal which is fed through the conductors 1008 and 1012 to the input 0 of the NAND gate 856, disabling the NAND gate 856 which disables the input D of the up-down counter 22 causing the counter to stop counting.

The 0 level signal 'on the conductor 1008 is also fed through the conductor 1010 to the R input of the flipflop 1004 causing the flip-flop 1004 to change state with a 1 level at its 6 output and a 0 level at its Q output. The 1 level at its fioutput is fed through the conductor 1016 to the input b of the NAND gate 852, and the 0 level at its Q output is fed through the conductor 1014 to the input b of the NAND gate 856 holding the NAND gate 856 in the disabled condition. As soon as the up-down counter 22 counted down from the count 506 the NAND gate 874 became disabled producing a l level at its output which was fed through the conductors 1000 and 1006 to the input 0 of the NAND gate 852.

With each of the inputs a, b and c of the NAND gate 852 at a 1 level, the NAND gate 852 is enabled, allowing the digital signal on the conductor 850 to pass through the NAND gate 852, and the conductor 858 to the U input of the up-down counter 22 causing the updown counter 22 to count up from the 6 count to the 506 count. This process of counting up and down between counts of 6 and 506 continues with the binary weighted outputs from the up-down counter 22 being fed through inverters to the inputs of the digital to analog converter 24. v

With the potentiometer 1026 adjusted as heretofore described to produce a zero voltage for the count of 256, the output of the sine shaping network 26 is an AC sinusoidal waveform having a positive peak voltage corresponding to the count of 506 and a negative peak voltage corresponding to the count of 6.

Because it takes 1,000 digital pulses to produce one cycle of the sine wave, the sine wave frequency will be one one-thousandth of the frequency of the synthesized digital signal on the conductor 546, so that with a digital frequency of 9.932678 MHz, the sine wave frequency is 9,932.678 Hz. The waveforms from the master synthesizer 12, can be fed into any number of frequency selectors to generate a plurality of frequencies. Because these frequencies are synthesized from the same source they are mutually coherent, so that the difierence between any one frequency and any other frequency always remains constant.

In summary, a system has been described to generate a plurality of coherent synthesized frequencies each of which may be selected from a wide range of frequencies. 1

Various changes and modifications may be made within the invention as will be readily apparent to those skilled in the art. Such changes and modifications are within the scope and teaching of this invention as defined by the claims appended hereto.

What is claimed is: p

l. A system for synthesizing an electrical signal having a frequency selected from a range of frequencies comprising a master synthesizer responsive to a constant frequency input for generating a plurality ofoutput waveforms of frequencies extending over a prescribed band of frequencies, means for selecting from the output waveforms a frequency to represent each digit of a selected synthesized frequency, and,

means for adding the selected frequencies to produce the selected synthesized frequency.

' 2. The system of claim 1 wherein the master synthesizer includes means for generating a first set of waveforms from the constant frequency input, and means for generating the plurality of output waveforms from the first set of waveforms.

3. The system of claim 2 wherein the first set of waveforms includes three waveforms of frequencies representing the ls, 2s, and 8s bits of a binary coded decimal counter, and the means for generating the output waveforms from the first set of waveforms includes logic means for generating the output waveforms from various combinations of the first set of waveforms.

4. The system of claim 1 including means for generating a complement waveform for. each of the output waveforms, and wherein the adding means includes means for adding pulses of the waveform complementary to the highest digit waveform in response to pulses of the other digit waveforms.

' 5. The system of claim 4 wherein the pulses of the complementary waveform are added to the highest digit waveform in response to pulses of the other digit waveforms with higher digit waveform frequencies taking precedence over lower digit waveform frequencies.

6. The system of claim 4 including means for generating a third set of waveforms of frequencies equal to the frequencies of the complementary waveforms but at a prescribed phase shift ahead of the complementary waveforms, and wherein the adding means is further responsive to the waveform of the third set of waveforms equal in frequency to the waveform complementary to the highest digit waveform.

7. The system of claim 1 wherein the output waveforms include frequencies representing the numhers I through 9 multiplied by a factor of 10.

8. The system of claim 7 wherein the factor of 10 is the same for each of the waveforms.

9. The system of claim 1 wherein the means for selecting a frequency to represent each digit includes a plurality of division networks for dividing the frequen-. cies of the output waveforms selected to represent the digits of the selected synthesized frequency by a factor of 10, the factor of 10 by which each selected frequency is divided depending on the digit it represents.

10. The system of claim 1 wherein the adding means includes a series of adding networks, one for each of the frequencies to be added to the highest digit frequency, and means for giving the addition of a higher frequency precedence over addition of a lower frequency.

11. The system of claim 1 wherein the selected synthesized signal is a pulse signal, and including means for generating a staircase waveform from the selected synthesized frequency.

12. The system of claim 11 wherein the staircase waveform generating means includes counter means for producing a'binary coded decimal encoded count between a predetermined upper count and a predetermined lower count in response to the pulses on the selected synthesized signal, and means for converting each count to a voltage level proportional to the count to produce a staircase waveform approximating a triangular wave.

13. The system of claim 12 including means for shaping the staircase waveform to produce a sinusoidal waveform.

14. A system'for synthesizing a plurality of mutually coherent electrical signals where the difference between the frequencies of any two of the signals remains constant overtime, each of the signals being of a frequency selected from a range of frequencies comprising a master synthesizer responsive to a constant frequency input for generating a plurality of output waveforms of frequencies extending over a prescribed band of frequencies, and a plurality of frequency selectors, each frequency selector comprising means for selecting from the output waveforms a frequency to represent each digit of a selected synthesized frequency, and means for adding the selected frequencies to produce the selected synthesized frequency, whereby slight changes in frequency of the constant frequency input produces corresponding changes in the frequencies synthesized therefrom with the synthesized signals being mutually coherent.

15. The system of claim 14 wherein the master synthesizer includes means for generating a first set of waveforms from the constant frequency input, and means for generating the output waveforms from the first set of waveforms.

16. A system for synthesizing an electrical signal comprised of pulses of a frequency selected from a range of frequencies, the system comprising a master oscillator for generating a pulse signal of a single frequency, the frequency of the master oscillator depending on the frequency of the signal to be synthesized, means for generating a plurality of output pulse signals from the single master oscillator pulse signal, the plurality of output pulse signals being of frequencies extending over a prescribed band of frequencies, means to select from the plurality of output pulse signals a signal for each digit of the selected synthesized signal, and means for adding the signals representing each digit to generate the selected synthesized signals.

17. The system of claim 16 wherein the digit selection means includes a plurality of logic switches, the plurality of output pulse signals generated from the master oscillator signal being fed as inputs to each of the logic switches, and means for selectively gating an input signal through selective ones of the logic switches, the output signals from the logic switches representing the digits of the selected synthesized signal.

18. The system of claim 17 including a plurality of division networks for dividing the frequencies of the output signals from the logic switches by factors of 10, the factor of 10 by which each frequency is divided depending on the digit it represents.

19. The system of claim 16 including means for generating a first set of pulse signals from the single master oscillator pulse signal and means for generating the plurality of output pulse signals from the first set of pulse signals.

20. The system of claim 16 including means for generating a complement pulse signal for each of the plurality of output pulse signals generated from the master oscillator signal, the complementary pulse signal having pulses where its complement has no pulses, and means for adding pulses of the signal complementary with the highest digit signal to the highest digit signal in response to pulses of the lower digit signals.

a 21. The system of claim 20 including means for generating a third set of signals of frequencies equal to the frequencies of the complementary signals but whose pulses are at a prescribed phase shift ahead of the pulses of the complementary waveforms, and wherein the adding means is further responsive to the signal of the third set of signals equal in frequency to the signal complementary to the highest digit signal.

22. The system of claim 21 wherein the phase shift is one master oscillator pulse.

23. The system of claim 22 wherein the adding means includes gating means responsive to the pulses on the signal of the third set of signals equal in frequency to the signal complementary to the highest digit signal for gating the pulses on the complementary signal for addition to the highest digit signal, the gating means being also responsive to the pulses of the lower digit signals, the number of pulses added being equal to the number of pulses of the lower digit signals, and the timing of the pulses added being determined by the signal of the third set of signals.

24. The system of claim 23 including gating means for adding a pulse in response to a higher digit signal pulse before adding a pulse in response to a lower digit signal pulse.

25. A system for synthesizing a plurality of mutually coherent signals, each signal comprising pulses of a frequency selected from a range of frequencies, the system comprising a master oscillator for generating a pulse signal of a single frequency, the frequency of the master oscillator depending on the maximum frequency to be synthesized, means for generating a first set of pulse signals from the master oscillator pulse signal, means for generating a second set of pulse signals from the first set of pulse signals of frequencies representing a multiple of the numbers 1 through 9, the multiple depending on the maximum frequency to be synthesized,

means for generating a complementary pulse signal for each of the second set of pulse signals, means for generating a third set of pulse signals equal in frequency to the complementary signals but at a prescribed phase shift ahead of the complementary signals, a plurality of frequency selectors, the number of frequency selectors depending on the number of coherent signals to be synthesized, each frequency selector comprising a plurality of logic switches, the number of logic switches depending on the number of digits in the signal to be synthesized, each of the second set of signals being fed as inputs to each of the logic switches, means for gating a selective signal from the second set of signals through selective ones of the logic switches, means into which the outputs of the logic switches are fed to divide each of the outputs from the logic switches separately by a factor of to produce signals representing each of the digits of a selected synthesized frequency, whereby each logic switch is set to gate a selected signal to represent a digit of the selected synthesized signal, and means for adding pulses on the signal complementary with the highest digit signal to the highest digit signal at times determined by the signal from the third set of signals equal in frequency to the complementary signal and in numbers determined by the number of pulses on the signals representing the remaining digits of the selected synthesized signal, and gating means to add a pulse in response to ahigher digit signal pulse before adding a pulse in response to a lower digit signal pulse, whereby slight changes in frequency of the master oscillator signal produces corresponding changes in the frequencies synthesized therefrom with the synthesized frequencies being mutually coherent.

'26. A method of synthesizing an electrical signal having a frequency selected from a range of frequencies comprising the steps of generating a first signal of constant frequency, synthesizing a set of second signals from the first signal of frequencies extending over a prescribed band of frequencies, each signal of the second set of signals being of a constant frequency, selecting from the frequencies of the second set of signals a frequency for each digit of the selected synthesized signal, and adding the selected frequencies together to produce the selected synthesized signal.

27. The method of claim 26 wherein after the generating step there is included the step of generating a first set of signals from the first constant frequency signal, and the step of synthesizing a set of second signals includes synthesizing the set of second signals from the first set of signals.

28. The system of claim 26 including the step of generating a complement signal for each of the second set of signals, and wherein the adding step includes adding pulses on the signal complementary with the highest digit signal to the highest digit signal in response to pulses on the lower digit signals.

29. The method of claim 28 including the step of generating a third set of waveforms of frequencies equal to the frequencies of the complementary waveforms but at a prescribed phase shift ahead of the complementary waveforms, and wherein the adding step further includes adding pulses on the waveform complementary with the highest digit waveform in response to the waveform of the third set of waveforms equal in frequency to the waveform complementary to the highest digit waveform.

30. The method of claim 26 wherein the selecting step further includes dividing the frequencies of the second set of signals selected to represent the digits of the selected synthesized signal by a factor of 10, the factor of 10 by which each selected frequency is divided depending on the digit it represents.

31. The method of claim 27 wherein the step of synthesizing the second set of signals from a first set of signals includes combining selective ones of the first set of signals in a logic circuit to synthesize the second set of signals.

32. A method of synthesizing a plurality of mutually coherent electrical signals where the difference between the frequencies of any two of the signals remains constant over time, each of the signals being of I a frequency selected from a range of frequencies, comprising the steps of generating a first waveform of constant frequency, synthesizing a set of second waveforms from the first waveform of frequencies extending over a prescribed band of frequencies, the frequency of each waveform in the second set of waveforms being constant, selecting from the second set of waveforms a frequency to represent each digit of a plurality of selected synthesized signals, and adding the selected frequencies for producing each selected synthesized signal, whereby slight changes in frequency of the first waveform produces corresponding changes in the frequencies of the signals synthesized therefrom with the selected synthesized signals being mutually coherent..

33. The method of claim 32 wherein after the generating step there is included the step of generating a first set of waveforms from the first waveform, and wherein the synthesizing step includes synthesizing the second set of waveforms from the first set of waveforms. v

34. The method of claim 31 wherein the selected synthesized signals are pulse signals, and including the step of generating a plurality of mutually coherent sinusoidal waveforms from the selected synthesized signals.

35. The method of claim 34 wherein the last mentioned step includes for each selected synthesized signal, generating signals corresponding to a binary coded decimal encoded count between a predetermined upper limit and a predetermined lower limit in response to the pulses on the selected synthesized frequency, generating a series of voltage levels in response to and in proportion to each count to produce a staircase waveform having a positive peak value corresponding to the predetermined upper count and a negative peak value corresponding to the predetermined lower count, and shaping the staircase waveform into a sinusoidal waveform. I

36. A method of synthesizing an electrical signal comprised of pulses of a frequency selected from a range of frequencies, comprising the steps of generating a first pulse signal of a single frequency, the frequency of the first pulse signal depending on the frequency of the signal to be synthesized, generating a second set of pulse signals from the single pulse signal of frequencies extending over a prescribed band of frequencies, each of the signals in the second set of signals being of constant frequency, selecting from the second set of pulse signals a signal for each digit of a selected synthesized signal, and adding the signals representing each digit to produce the selected synthesized signal.

37. The method of claim 36 including the steps of feeding the second set of signals as inputs to each of a plurality of logic switches, and wherein the selecting step includes selectively gating an input signal through selective ones of the logic switches.

38. The method of claim 37 including'the step of dividing the frequencies of the gated signals at the outputs of the logic switches by factors of 10, the factors of 10 by which each frequency is divided depending on the digit it represents.

39. The method of can 36 including the step of generating a complement pulse signal for each of the second set of pulse signals, and wherein the adding step includes adding pulses of the signal complementary 1 with the highest digit signal in response to pulses of the lower digit signals to the highest digit signal.

40. The method of claim 39 including the step of generating a third set of signals with frequencies equal to the frequencies of the complementary signals but whose pulses are at a prescribed phase shift ahead of the pulses of the complementary waveform, and wherein the adding step further includes adding pulses of the complementary signal in'response to the signal in the third set of signals equal in frequency to thecomplementary signal.

41. The method of claim 40 wherein the adding step further includes gating pulses on the complementary signal for addition to the highest digit signal in response to pulses on the signal of the third set of signals equal in frequency to the signal complementary to the highest digit signal, and to pulses on the lower digit signals, the number of pulses added being equal to the number of pulses on the lower digit signals, and the timing of the pulses added being determined by the pulses on the signal of the third set of signals.

42. The method of claim 39 wherein a pulse is added in response to a higher digit signal pulse before a pulse is added in response to a lower digit signal pulse.

43. A method for synthesizing a plurality of mutually coherent signals each signal comprising pulses of a frequency selected from a range of frequencies, comprising the steps of generating a first signal of constant frequency, the frequency of the first signal depending on the maximum frequency of the mutually coherent signals to be synthesized, generating a first set of pulse signals from the first signal, generating a second set of pulse signals from the first set of pulse signals, the second set of pulse signals being of frequencies representing a multiple of the numbers 1 through 9, the multiple depending on the maximum frequency of the mutually coherent signalsto be synthesized, generating a complementary pulse signal for each of the second set of pulse signals, generating a third set of pulse signals equal in frequency to the complementary pulse signals but at a prescribed phase shift ahead of the compleinentary signals, feeding each of the second set of signals as inputs to each of a plurality of logic switches, the number of logic switches depending on the number of digits in the signals to be synthesized, gating a selective signal from the second set of signals through selected ones of the logic switches, dividing each of the gated signals'separately by a factor of 10 to produce signals representing each of the digits of the selected synthesized signals, whereby each logic switch is set to gate a selected signal to represent a digit of each of the selected synthesized signals, and adding pulses of the signals complementary with the highest digit signals of the selected synthesized signals at times determined by signals of the third set of signals equal in frequency to the complementary signals and in numbers determined by the number of pulses on the signals representing the remaining digits of each of the selected synthesized signals, so that in synthesizing each selected signal a pulse is added in response to a pulse on a higher digit signal before a pulse on a lower digit signal, whereby sli tchan es in fre ue c oft efirst si nal rod ces co ri' espon mg changes i n the t r equencie s syii thesi zed therefrom with the synthesized signals being mutuall coherent.

44. A method of synthesizing an electrical signal hav- 4 each of the second set of signals, generating a set of enable signals equal in frequency to the complementary signals but at a prescribed phase shift ahead of the complementary signals, selecting from the second set .of signals a frequency for each digit of the selected synthesized signal, and adding each of the selected frequencies representing the lower digits to the highest digit frequency in a plurality of adding networks, the adding step further comprising the steps of recognizing each pulse on the signals to beadded to the highest digit frequency, for each pulse recognized, recognizing the next pulse on the enable signal equal in frequency to the signal complementary to the highest digit signal, enabling a gate in response to the pulse on the enable signal, with the gate enabled, gating the next pulse on the signal complementary to the highest digit signal to an adding gate, adding the pulse on the complementary signal to the highest digit signal, and blocking the recognition of a pulse on a lower digit signal whenever a pulse on a higher digit signal appears giving higher digit signals precedence over lower digit signals,

whereby over a time span of one second all of the pulses that appear on the lower digit signals will be added to the highest digit signal. 

1. A system for synthesizing an electrical signal having a frequency selected from a range of frequencies comprising a master synthesizer responsive to a constant frequency input for generating a plurality of output waveforms of frequencies extending over a prescribed band of frequencies, means for selecting from the output waveforms a frequency to represent each digit of a selected synthesized frequency, and means for adding the selected frequencies to produce the selected synthesized frequency.
 2. The system of claim 1 wherein the master synthesizer includes means for generating a first set of waveforms from the constant frequency input, and means for generating the plurality of output waveforms from the first set of waveforms.
 3. The system of claim 2 wherein the first set of waveforms includes three waveforms of frequencies representing the 1''s, 2''s, and 8''s bits of a binary coded decimal counter, and the means for generating the output waveforms from the first set of waveforms includes logic means for generating the output waveforms from various combinations of the first set of waveforms.
 4. The system of claim 1 including means for generating a complement waveform for each of the output waveforms, and wherein the adding means includes means for adding pulses of the waveform complementary to the highest digit waveform in response to pulses of the other digit waveforms.
 5. The system of claim 4 wherein the pulses of the complementary waveform are added to the highest digit waveform in response to pulses of the other digit waveforms with higher digit waveform frequencies taking precedence over lower digit waveform frequencies.
 6. The system of claim 4 including means for generating a third set of waveforms of frequencies equal to the frequencies of the complementary waveforms but at a prescribed phase shift ahead of the complementary waveforms, and wherein the adding means is further responsive to the waveform of the third set of waveforms equal in frequency to the waveform complementary to the highest digit waveform.
 7. The system of claim 1 wherein the output Waveforms include frequencies representing the numbers 1 through 9 multiplied by a factor of
 10. 8. The system of claim 7 wherein the factor of 10 is the same for each of the waveforms.
 9. The system of claim 1 wherein the means for selecting a frequency to represent each digit includes a plurality of division networks for dividing the frequencies of the output waveforms selected to represent the digits of the selected synthesized frequency by a factor of 10, the factor of 10 by which each selected frequency is divided depending on the digit it represents.
 10. The system of claim 1 wherein the adding means includes a series of adding networks, one for each of the frequencies to be added to the highest digit frequency, and means for giving the addition of a higher frequency precedence over addition of a lower frequency.
 11. The system of claim 1 wherein the selected synthesized signal is a pulse signal, and including means for generating a staircase waveform from the selected synthesized frequency.
 12. The system of claim 11 wherein the staircase waveform generating means includes counter means for producing a binary coded decimal encoded count between a predetermined upper count and a predetermined lower count in response to the pulses on the selected synthesized signal, and means for converting each count to a voltage level proportional to the count to produce a staircase waveform approximating a triangular wave.
 13. The system of claim 12 including means for shaping the staircase waveform to produce a sinusoidal waveform.
 14. A system for synthesizing a plurality of mutually coherent electrical signals where the difference between the frequencies of any two of the signals remains constant over time, each of the signals being of a frequency selected from a range of frequencies comprising a master synthesizer responsive to a constant frequency input for generating a plurality of output waveforms of frequencies extending over a prescribed band of frequencies, and a plurality of frequency selectors, each frequency selector comprising means for selecting from the output waveforms a frequency to represent each digit of a selected synthesized frequency, and means for adding the selected frequencies to produce the selected synthesized frequency, whereby slight changes in frequency of the constant frequency input produces corresponding changes in the frequencies synthesized therefrom with the synthesized signals being mutually coherent.
 15. The system of claim 14 wherein the master synthesizer includes means for generating a first set of waveforms from the constant frequency input, and means for generating the output waveforms from the first set of waveforms.
 16. A system for synthesizing an electrical signal comprised of pulses of a frequency selected from a range of frequencies, the system comprising a master oscillator for generating a pulse signal of a single frequency, the frequency of the master oscillator depending on the frequency of the signal to be synthesized, means for generating a plurality of output pulse signals from the single master oscillator pulse signal, the plurality of output pulse signals being of frequencies extending over a prescribed band of frequencies, means to select from the plurality of output pulse signals a signal for each digit of the selected synthesized signal, and means for adding the signals representing each digit to generate the selected synthesized signals.
 17. The system of claim 16 wherein the digit selection means includes a plurality of logic switches, the plurality of output pulse signals generated from the master oscillator signal being fed as inputs to each of the logic switches, and means for selectively gating an input signal through selective ones of the logic switches, the output signals from the logic switches representing the digits of the selected synthesized signal.
 18. The system of claim 17 including a plurality of division networks for dividing the frequencieS of the output signals from the logic switches by factors of 10, the factor of 10 by which each frequency is divided depending on the digit it represents.
 19. The system of claim 16 including means for generating a first set of pulse signals from the single master oscillator pulse signal and means for generating the plurality of output pulse signals from the first set of pulse signals.
 20. The system of claim 16 including means for generating a complement pulse signal for each of the plurality of output pulse signals generated from the master oscillator signal, the complementary pulse signal having pulses where its complement has no pulses, and means for adding pulses of the signal complementary with the highest digit signal to the highest digit signal in response to pulses of the lower digit signals.
 21. The system of claim 20 including means for generating a third set of signals of frequencies equal to the frequencies of the complementary signals but whose pulses are at a prescribed phase shift ahead of the pulses of the complementary waveforms, and wherein the adding means is further responsive to the signal of the third set of signals equal in frequency to the signal complementary to the highest digit signal.
 22. The system of claim 21 wherein the phase shift is one master oscillator pulse.
 23. The system of claim 22 wherein the adding means includes gating means responsive to the pulses on the signal of the third set of signals equal in frequency to the signal complementary to the highest digit signal for gating the pulses on the complementary signal for addition to the highest digit signal, the gating means being also responsive to the pulses of the lower digit signals, the number of pulses added being equal to the number of pulses of the lower digit signals, and the timing of the pulses added being determined by the signal of the third set of signals.
 24. The system of claim 23 including gating means for adding a pulse in response to a higher digit signal pulse before adding a pulse in response to a lower digit signal pulse.
 25. A system for synthesizing a plurality of mutually coherent signals, each signal comprising pulses of a frequency selected from a range of frequencies, the system comprising a master oscillator for generating a pulse signal of a single frequency, the frequency of the master oscillator depending on the maximum frequency to be synthesized, means for generating a first set of pulse signals from the master oscillator pulse signal, means for generating a second set of pulse signals from the first set of pulse signals of frequencies representing a multiple of the numbers 1 through 9, the multiple depending on the maximum frequency to be synthesized, means for generating a complementary pulse signal for each of the second set of pulse signals, means for generating a third set of pulse signals equal in frequency to the complementary signals but at a prescribed phase shift ahead of the complementary signals, a plurality of frequency selectors, the number of frequency selectors depending on the number of coherent signals to be synthesized, each frequency selector comprising a plurality of logic switches, the number of logic switches depending on the number of digits in the signal to be synthesized, each of the second set of signals being fed as inputs to each of the logic switches, means for gating a selective signal from the second set of signals through selective ones of the logic switches, means into which the outputs of the logic switches are fed to divide each of the outputs from the logic switches separately by a factor of 10 to produce signals representing each of the digits of a selected synthesized frequency, whereby each logic switch is set to gate a selected signal to represent a digit of the selected synthesized signal, and means for adding pulses on the signal complementary with the highest digit signal to the highest digit signal at times determined by the signal from the third set of signAls equal in frequency to the complementary signal and in numbers determined by the number of pulses on the signals representing the remaining digits of the selected synthesized signal, and gating means to add a pulse in response to a higher digit signal pulse before adding a pulse in response to a lower digit signal pulse, whereby slight changes in frequency of the master oscillator signal produces corresponding changes in the frequencies synthesized therefrom with the synthesized frequencies being mutually coherent.
 26. A method of synthesizing an electrical signal having a frequency selected from a range of frequencies comprising the steps of generating a first signal of constant frequency, synthesizing a set of second signals from the first signal of frequencies extending over a prescribed band of frequencies, each signal of the second set of signals being of a constant frequency, selecting from the frequencies of the second set of signals a frequency for each digit of the selected synthesized signal, and adding the selected frequencies together to produce the selected synthesized signal.
 27. The method of claim 26 wherein after the generating step there is included the step of generating a first set of signals from the first constant frequency signal, and the step of synthesizing a set of second signals includes synthesizing the set of second signals from the first set of signals.
 28. The system of claim 26 including the step of generating a complement signal for each of the second set of signals, and wherein the adding step includes adding pulses on the signal complementary with the highest digit signal to the highest digit signal in response to pulses on the lower digit signals.
 29. The method of claim 28 including the step of generating a third set of waveforms of frequencies equal to the frequencies of the complementary waveforms but at a prescribed phase shift ahead of the complementary waveforms, and wherein the adding step further includes adding pulses on the waveform complementary with the highest digit waveform in response to the waveform of the third set of waveforms equal in frequency to the waveform complementary to the highest digit waveform.
 30. The method of claim 26 wherein the selecting step further includes dividing the frequencies of the second set of signals selected to represent the digits of the selected synthesized signal by a factor of 10, the factor of 10 by which each selected frequency is divided depending on the digit it represents.
 31. The method of claim 27 wherein the step of synthesizing the second set of signals from a first set of signals includes combining selective ones of the first set of signals in a logic circuit to synthesize the second set of signals.
 32. A method of synthesizing a plurality of mutually coherent electrical signals where the difference between the frequencies of any two of the signals remains constant over time, each of the signals being of a frequency selected from a range of frequencies, comprising the steps of generating a first waveform of constant frequency, synthesizing a set of second waveforms from the first waveform of frequencies extending over a prescribed band of frequencies, the frequency of each waveform in the second set of waveforms being constant, selecting from the second set of waveforms a frequency to represent each digit of a plurality of selected synthesized signals, and adding the selected frequencies for producing each selected synthesized signal, whereby slight changes in frequency of the first waveform produces corresponding changes in the frequencies of the signals synthesized therefrom with the selected synthesized signals being mutually coherent.
 33. The method of claim 32 wherein after the generating step there is included the step of generating a first set of waveforms from the first waveform, and wherein the synthesizing step includes synthesizing the second set of waveforms from the first set of waveforms.
 34. The method of claim 31 wherein the seleCted synthesized signals are pulse signals, and including the step of generating a plurality of mutually coherent sinusoidal waveforms from the selected synthesized signals.
 35. The method of claim 34 wherein the last mentioned step includes for each selected synthesized signal, generating signals corresponding to a binary coded decimal encoded count between a predetermined upper limit and a predetermined lower limit in response to the pulses on the selected synthesized frequency, generating a series of voltage levels in response to and in proportion to each count to produce a staircase waveform having a positive peak value corresponding to the predetermined upper count and a negative peak value corresponding to the predetermined lower count, and shaping the staircase waveform into a sinusoidal waveform.
 36. A method of synthesizing an electrical signal comprised of pulses of a frequency selected from a range of frequencies, comprising the steps of generating a first pulse signal of a single frequency, the frequency of the first pulse signal depending on the frequency of the signal to be synthesized, generating a second set of pulse signals from the single pulse signal of frequencies extending over a prescribed band of frequencies, each of the signals in the second set of signals being of constant frequency, selecting from the second set of pulse signals a signal for each digit of a selected synthesized signal, and adding the signals representing each digit to produce the selected synthesized signal.
 37. The method of claim 36 including the steps of feeding the second set of signals as inputs to each of a plurality of logic switches, and wherein the selecting step includes selectively gating an input signal through selective ones of the logic switches.
 38. The method of claim 37 including the step of dividing the frequencies of the gated signals at the outputs of the logic switches by factors of 10, the factors of 10 by which each frequency is divided depending on the digit it represents.
 39. The method of claim 36 including the step of generating a complement pulse signal for each of the second set of pulse signals, and wherein the adding step includes adding pulses of the signal complementary with the highest digit signal in response to pulses of the lower digit signals to the highest digit signal.
 40. The method of claim 39 including the step of generating a third set of signals with frequencies equal to the frequencies of the complementary signals but whose pulses are at a prescribed phase shift ahead of the pulses of the complementary waveform, and wherein the adding step further includes adding pulses of the complementary signal in response to the signal in the third set of signals equal in frequency to the complementary signal.
 41. The method of claim 40 wherein the adding step further includes gating pulses on the complementary signal for addition to the highest digit signal in response to pulses on the signal of the third set of signals equal in frequency to the signal complementary to the highest digit signal, and to pulses on the lower digit signals, the number of pulses added being equal to the number of pulses on the lower digit signals, and the timing of the pulses added being determined by the pulses on the signal of the third set of signals.
 42. The method of claim 39 wherein a pulse is added in response to a higher digit signal pulse before a pulse is added in response to a lower digit signal pulse.
 43. A method for synthesizing a plurality of mutually coherent signals each signal comprising pulses of a frequency selected from a range of frequencies, comprising the steps of generating a first signal of constant frequency, the frequency of the first signal depending on the maximum frequency of the mutually coherent signals to be synthesized, generating a first set of pulse signals from the first signal, generating a second set of pulse signals from the first set of pulse signals, the second set of pulse signals being of Frequencies representing a multiple of the numbers 1 through 9, the multiple depending on the maximum frequency of the mutually coherent signals to be synthesized, generating a complementary pulse signal for each of the second set of pulse signals, generating a third set of pulse signals equal in frequency to the complementary pulse signals but at a prescribed phase shift ahead of the complementary signals, feeding each of the second set of signals as inputs to each of a plurality of logic switches, the number of logic switches depending on the number of digits in the signals to be synthesized, gating a selective signal from the second set of signals through selected ones of the logic switches, dividing each of the gated signals separately by a factor of 10 to produce signals representing each of the digits of the selected synthesized signals, whereby each logic switch is set to gate a selected signal to represent a digit of each of the selected synthesized signals, and adding pulses of the signals complementary with the highest digit signals of the selected synthesized signals at times determined by signals of the third set of signals equal in frequency to the complementary signals and in numbers determined by the number of pulses on the signals representing the remaining digits of each of the selected synthesized signals, so that in synthesizing each selected signal a pulse is added in response to a pulse on a higher digit signal before a pulse on a lower digit signal, whereby slight changes in frequency of the first signal produces corresponding changes in the frequencies synthesized therefrom with the synthesized signals being mutually coherent.
 44. A method of synthesizing an electrical signal having a frequency selected from a range of frequencies comprising the steps of generating a first signal of constant frequency, generating a set of second signals from the first signal, the set of second signals being of frequencies extending over a prescribed band of frequencies, generating a complementary signal for each of the second set of signals, generating a set of enable signals equal in frequency to the complementary signals but at a prescribed phase shift ahead of the complementary signals, selecting from the second set of signals a frequency for each digit of the selected synthesized signal, and adding each of the selected frequencies representing the lower digits to the highest digit frequency in a plurality of adding networks, the adding step further comprising the steps of recognizing each pulse on the signals to be added to the highest digit frequency, for each pulse recognized, recognizing the next pulse on the enable signal equal in frequency to the signal complementary to the highest digit signal, enabling a gate in response to the pulse on the enable signal, with the gate enabled, gating the next pulse on the signal complementary to the highest digit signal to an adding gate, adding the pulse on the complementary signal to the highest digit signal, and blocking the recognition of a pulse on a lower digit signal whenever a pulse on a higher digit signal appears giving higher digit signals precedence over lower digit signals, whereby over a time span of one second all of the pulses that appear on the lower digit signals will be added to the highest digit signal. 